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FEATURES On-Chip Latches for Both DACs +5 V to +15 V Operation DACs Matched to 1% Four Quadrant Multiplication TTL/CMOS Compatible Latch Free (Protection Schottkys not Required) APPLICATIONS Digital Control of: Gain/Attenuation Filter Parameters Stereo Audio Circuits X-Y Graphics
VDD DB0 DATA INPUTS DB7
CMOS Dual 8-Bit Buffered Multiplying DAC AD7528
FUNCTIONAL BLOCK DIAGRAM
VREF A RFB A INPUT BUFFER OUT A LATCH DAC A
AGND DAC A/ DAC B CS WR LATCH DGND DAC B CONTROL LOGIC
AD7528
RFB B OUT B
VREF B
GENERAL DESCRIPTION
ORDERING GUIDE1 Model2 AD7528JN AD7528KN AD7528LN AD7528JP AD7528KP AD7528LP AD7528JR AD7528KR AD7528LR AD7528AQ AD7528BQ AD7528CQ AD7528SQ AD7528TQ AD7528UQ Temperature Ranges -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -55C to +125C -55C to +125C -55C to +125C Relative Gain Accuracy Error 1 LSB 1/2 LSB 1/2 LSB 1 LSB 1/2 LSB 1/2 LSB 1 LSB 1/2 LSB 1/2 LSB 1 LSB 1/2 LSB 1/2 LSB 1 LSB 1/2 LSB 1/2 LSB 4 LSB 2 LSB 1 LSB 4 LSB 2 LSB 1 LSB 4 LSB 2 LSB 1 LSB 4 LSB 2 LSB 1 LSB 4 LSB 2 LSB 1 LSB Package Options 3 N-20 N-20 N-20 P-20A P-20A P-20A R-20 R-20 R-20 Q-20 Q-20 Q-20 Q-20 Q-20 Q-20
The AD7528 is a monolithic dual 8-bit digital/analog converter featuring excellent DAC-to-DAC matching. It is available in skinny 0.3" wide 20-lead DIPs and in 20-lead surface mount packages. Separate on-chip latches are provided for each DAC to allow easy microprocessor interface. Data is transferred into either of the two DAC data latches via a common 8-bit TTL/CMOS compatible input port. Control input DAC A/DAC B determines which DAC is to be loaded. The AD7528's load cycle is similar to the write cycle of a random access memory and the device is bus compatible with most 8-bit microprocessors, including 6800, 8080, 8085, Z80. The device operates from a +5 V to +15 V power supply, dissipating only 20 mW of power. Both DACs offer excellent four quadrant multiplication characteristics with a separate reference input and feedback resistor for each DAC.
PRODUCT HIGHLIGHTS
1. DAC-to-DAC matching: since both of the AD7528 DACs are fabricated at the same time on the same chip, precise matching and tracking between DAC A and DAC B is inherent. The AD7528's matched CMOS DACs make a whole new range of applications circuits possible, particularly in the audio, graphics and process control areas. 2. Small package size: combining the inputs to the on-chip DAC latches into a common data bus and adding a DAC A/DAC B select line has allowed the AD7528 to be packaged in either a small 20-lead DIP, SOIC or PLCC. REV. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
NOTES 1 Analog Devices reserves the right to ship side-brazed ceramic in lieu of cerdip. Parts will be marked with cerdip designator "Q." 2 Processing to MIL-STD-883C, Class B is available. To order, add suffix "/883B" to part number. For further information, see Analog Devices' 1990 Military Products Databook. 3 N = Plastic DIP; P = Plastic Leaded Chip Carrier; Q = Cerdip; R = SOIC.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 1998
AD7528-SPECIFICATIONS (V
Parameter STATIC PERFORMANCE2 Resolution Relative Accuracy Version1 All J, A, S K, B, T L, C, U All J, A, S K, B, T L, C, U TA = +25C 8 1 1/2 1/2 1 4 2 1 0.007 50 50 8 15 1
REF A
= VREF B = +10 V; OUT A = OUT B = O V unless otherwise noted)
VDD = +15 V TA= +25C TMIN, TMAX 8 1 1/2 1/2 1 4 2 1 0.0035 50 50 8 15 1 8 1 1/2 1/2 1 5 3 1 0.0035 200 200 8 15 1 Units Bits LSB max LSB max LSB max LSB max LSB max LSB max LSB max Test Conditions/Comments
V DD = +5 V TMIN, TMAX 8 1 1/2 1/2 1 6 4 3 0.007 400 400 8 15 1
This is an Endpoint Linearity Specification
Differential Nonlinearity Gain Error
All Grades Guaranteed Monotonic Over Full Operating Temperature Range Measured Using Internal R FB A and RFB B Both DAC Latches Loaded with 11111111 Gain Error is Adjustable Using Circuits of Figures 4 and 5
Gain Temperature Coefficient3 Gain/Temperature Output Leakage Current OUT A (Pin 2) OUT B (Pin 20) Input Resistance (V REF A, V REF B) VREF A/V REF B Input Resistance Match DIGITAL INPUTS4 Input High Voltage VIH Input Low Voltage VIL Input Current IIN Input Capacitance DB0-DB7 WR, CS, DAC A/DAC B SWITCHING CHARACTERISTICS 3 Chip Select to Write Set Up Time tCS Chip Select to Write Hold Time tCH DAC Select to Write Set Up Time tAS DAC Select to Write Hold Time tAH Data Valid to Write Set Up Time tDS Data Valid to Write Hold Time tDH Write Pulsewidth tWR POWER SUPPLY IDD
All All All All
%/C max nA max nA max k min k max % max DAC Latches Loaded with 00000000 Input Resistance TC = -300 ppm/C, Typical Input Resistance is 11 k
All
All All All All All
2.4 0.8 1 10 15
2.4 0.8 10 10 15
13.5 1.5 1 10 15
13.5 1.5 10 10 15
V min V max A max pF max pF max See Timing Diagram VIN = 0 or V DD
All All All All All All All All All
90 0 90 0 80 0 90 2 100
100 0 100 0 90 0 100 2 500
60 10 60 10 30 0 60 2 100
80 15 80 15 40 0 80 2 500
ns min ns min ns min ns min ns min ns min ns min mA max A max See Figure 3 All Digital Inputs VIL or VIH All Digital Inputs 0 V or V DD
AC PERFORMANCE CHARACTERISTICS5 Output Amplifiers)
V DD = +5 V Parameter DC SUPPLY REJECTION (GAIN/VDD) CURRENT SETTLING TIME2 Version1 TA = +25C All All 0.02 350 0.04 400 0.01 180
(Measured Using Recommended P.C. Board Layout (Figure 7) and AD644 as
VDD = +15 V Test Conditions/Comments To 1/2 LSB. OUT A/OUT B Load = 100 . WR = CS = 0 V. DB0-DB7 = 0 V to VDD or VDD to 0 V VREF A = VREF B = +10 V OUT A, OUT B Load = 100 C EXT = 13 pF WR = CS = 0 V DB0-DB7 = 0 V to VDD or VDD to 0 V For Code Transition 00000000 to 11111111 DAC Latches Loaded with 00000000 DAC Latches Loaded with 11111111 0.02 200 % per % max V DD = 5% ns max
TMIN, TMAX TA= +25C TMIN, TMAX Units
PROPAGATION DELAY (From Digital Input to 90% of Final Analog Output Current)
All
220
270
80
100
ns max
DIGITAL-TO-ANALOG GLITCH IMPULSE All OUTPUT CAPACITANCE COUT A COUT B COUT A COUT B AC FEEDTHROUGH 6 VREF A to OUT A VREF B to OUT B All
160 50 50 120 120 -70 -70 50 50 120 120 -65 -65
440 50 50 120 120 -70 -70 50 50 120 120 -65 -65
nV sec typ pF max pF max pF max pF max dB max dB max
All
VREF A, VREF B = 20 V p-p Sine Wave @ 100 kHz
-2-
REV. B
AD7528
V DD = +5 V Parameter CHANNEL-TO-CHANNEL ISOLATION VREF A to OUT B VREF B to OUT A DIGITAL CROSSTALK HARMONIC DISTORTlON All All Version1 TA = +25C All -77 -77 30 -85 VDD = +15 V Test Conditions/Comments Both DAC Latches Loaded with 11111111. VREF A = 20 V p-p Sine Wave @ 100 kHz VREF B = 0 V see Figure 6. VREF A = 20 V p-p Sine Wave @ 100 kHz VREF A = 0 V see Figure 6. Measured for Code Transition 00000000 to 11111111 VIN = 6 V rms @ 1 kHz TMIN, TMAX TA= +25C TMIN, TMAX Units -77 -77 60 -85 dB typ dB typ nV sec typ dB typ
NOTES 1 Temperature Ranges are J, K, L Versions: -40C to +85C A, B, C Versions: -40C to +85C S, T, U Versions: -55C to +125C 2 Specifications applies to both DACs in AD7528. 3 Guaranteed by design but not production tested. 4 Logic inputs are MOS Gates. Typical input current (+25C) is less than 1 nA. 5 These characteristics are for design guidance only and are not subject to test. 6 Feedthrough can be further reduced by connecting the metal lid on the ceramic package (suffix D) to DGND. Specifications subject to change without notice.
AD7528, ideal maximum output is VREF - 1 LSB. Gain error of both DACs is adjustable to zero with external resistance.
Output Capacitance
Capacitance from OUT A or OUT B to AGND.
Digital to Analog Glitch lmpulse
ABSOLUTE MAXIMUM RATINGS
(TA = +25C unless otherwise noted)
VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V, +17 V VDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V, +17 V AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . VDD + 0.3 V DGND to AGND . . . . . . . . . . . . . . . . . . . . . . . . VDD + 0.3 V Digital Input Voltage to DGND . . . . . . . -0.3 V, VDD + 0.3 V VPIN2, V PIN20 to AGND . . . . . . . . . . . . . . -0.3 V, VDD + 0.3 V VREF A, VREF B to AGND . . . . . . . . . . . . . . . . . . . . . . . 25 V VRFB A, VRFB B to AGND . . . . . . . . . . . . . . . . . . . . . . . 25 V Power Dissipation (Any Package) to +75C . . . . . . . 450 mW Derates above +75C by . . . . . . . . . . . . . . . . . . . 6 mW/C Operating Temperature Range Commercial (J, K, L) Grades . . . . . . . . . . . -40C to +85C Industrial (A, B, C) Grades . . . . . . . . . . . . -40C to +85C Extended (S, T, U) Grades . . . . . . . . . . . -55C to +125C Storage Temperature . . . . . . . . . . . . . . . . . . -65C to +150C Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . . +300C
CAUTION:
The amount of charge injected from the digital inputs to the analog output when the inputs change state. This is normally specified as the area of the glitch in either pA-secs or nV-secs depending upon whether the glitch is measured as a current or voltage signal. Glitch impulse is measured with VREF A, VREF B = AGND.
Propagation Delay
This is a measure of the internal delays of the circuit and is defined as the time from a digital input change to the analog output current reaching 90% of its final value.
Channel-to-Channel Isolation
The proportion of input signal from one DAC's reference input which appears at the output of the other DAC, expressed as a ratio in dB.
Digital Crosstalk
The glitch energy transferred to the output of one converter due to a change in digital input code to the other converter. Specified in nV secs.
PIN CONFIGURATIONS PLCC
OUT A OUT B
20
1. ESD sensitive device. The digital control inputs are diode protected; however, permanent damage may occur on unconnected devices subjected to high energy electrostatic fields. Unused devices must be stored in conductive foam or shunts. 2. Do not insert this device into powered sockets. Remove power before insertion or removal.
TERMINOLOGY Relative Accuracy
VREF A 4 DGND 5 DAC A/DAC B 6 (MSB) DB7 7 DB6 8
AGND
RFB A
3
2
1
PIN 1 IDENTIFIER
RFB B
19 18 17
VREF B VDD WR CS DB0 (LSB)
AD7528
TOP VIEW (Not to Scale)
16 15 14
Relative accuracy or endpoint nonlinearity is a measure of the maximum deviation from a straight line passing through the endpoints of the DAC transfer function. It is measured after adjusting for zero and full scale and is normally expressed in LSBs or as a percentage of full scale reading.
Differential Nonlinearity
9
10
11
12
13
DB5
DB4
DB3
DB2
DB1
DIP, SOIC
AGND 1 OUT A
2 20 19 18 17 16
OUT B RFB B VREF B VDD
RFB A 3 VREF A 4 DGND
5
Differential nonlinearity is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of 1 LSB max over the operating temperature range ensures monotonicity.
Gain Error
DAC A/DAC B 6
WR AD7528 TOP VIEW 15 CS (Not to Scale) 14 DB0 (LSB) (MSB) DB7 7 DB6 8 DB5 9 DB4 10
13 12 11
DB1 DB2 DB3
Gain error or full-scale error is a measure of the output error between an ideal DAC and the actual device output. For the REV. B -3-
AD7528
INTERFACE LOGIC INFORMATION DAC Selection:
Both DAC latches share a common 8-bit input port. The control input DAC A/DAC B selects which DAC can accept data from the input port.
Mode Selection:
Figure 1. An inverted R-2R ladder structure is used, that is, binary weighted currents are switched between the DAC output and AGND thus maintaining fixed currents in each ladder leg independent of switch state.
EQUIVALENT CIRCUIT ANALYSIS
Inputs CS and WR control the operating mode of the selected DAC. See Mode Selection Table below.
Write Mode:
When CS and WR are both low the selected DAC is in the write mode. The input data latches of the selected DAC are transparent and its analog output responds to activity on DB0-DB7.
Hold Mode:
Figure 2 shows an approximate equivalent circuit for one of the AD7528's D/A converters, in this case DAC A. A similar equivalent circuit can be drawn for DAC B. Note that AGND (Pin 1) is common for both DAC A and DAC B. The current source ILEAKAGE is composed of surface and junction leakages and, as with most semiconductor devices, approximately doubles every 10C. The resistor RO as shown in Figure 2 is the equivalent output resistance of the device which varies with input code (excluding all 0s code) from 0.8 R to 2 R. R is typically 11 k. COUT is the capacitance due to the N-channel switches and varies from about 50 pF to 120 pF depending upon the digital input. g(VREF A, N) is the Thevenin equivalent voltage generator due to the reference input voltage VREF A and the transfer function of the R-2R ladder.
R RO g(VREF A, N) I LKG COUT AGND RFB A OUT A
The selected DAC latch retains the data which was present on DB0-DB7 just prior to CS or WR assuming a high state. Both analog outputs remain at the values corresponding to the data in their respective latches.
Mode Selection Table
DAC A/DAC B L H X X CS L L H X WR L L X H DAC A WRITE HOLD HOLD HOLD DAC B HOLD WRITE HOLD HOLD
L = Low State; H = High State; X = Don't Care.
Figure 2. Equivalent Analog Output Circuit of DAC A
WRITE CYCLE TIMING DIAGRAM
CHIP SELECT
t CS
t CH
CIRCUIT INFORMATION-DIGITAL SECTION
VDD 0
DAC A/DAC B
t AS t WR
t AH
VDD 0 VDD 0
WRITE
t DS
DATA IN (DB0 - DB7)
VIH VIL
t DH
VDD 0
The input buffers are simple CMOS inverters designed such that when the AD7528 is operated with VDD = 5 V, the buffer converts TTL input levels (2.4 V and 0.8 V) into CMOS logic levels. When VIN is in the region of 2.0 volts to 3.5 volts the input buffers operate in their linear region and pass a quiescent current, see Figure 3. To minimize power supply currents it is recommended that the digital input voltages be as close to the supply rails (VDD and DGND) as is practically possible. The AD7528 may be operated with any supply voltage in the range 5 VDD 15 volts. With VDD = +15 V the input logic levels are CMOS compatible only, i.e., 1.5 V and 13.5 V.
9 800 IDD A (VDD = +5V) 700 600 500 400 300 200 100 VDD = +5V VDD = +15V TA = +25 C ALL DIGITAL INPUTS TIED TOGETHER 8 IDD mA (VDD = +15V) 7 6 5 4 3 2 1 0 1 2 3 4 5 6 7 8 VIN - Volts 9 10 11 12 13 14
DATA IN STABLE
NOTES: 1. ALL INPUT SIGNAL RISE AND FALL TIMES MEASURED FROM 10% TO 90% OF VDD. VDD = +5V, t r = t f = 20ns; VDD = +15V, t r = t f = 40ns; VIH + VIL 2. TIMING MEASUREMENT REFERENCE LEVEL IS 2
CIRCUIT INFORMATION--D/A SECTION
The AD7528 contains two identical 8-bit multiplying D/A converters, DAC A and DAC B. Each DAC consists of a highly stable thin film R-2R ladder and eight N-channel current steering switches. A simplified D/A circuit for DAC A is shown in
R VREF A 2R S1 2R S2 2R S3 2R S8 2R R RFB A OUT A AGND DAC A DATA LATCHES AND DRIVERS R R
Figure 3. Typical Plots of Supply Current, IDD vs. Logic Input Voltage VIN, for VDD = +5 V and +15 V
Figure 1. Simplified Functional Circuit for DAC A
-4-
REV. B
AD7528
VIN A ( 10V) R11 R21 VDD DB0 DATA INPUTS DB7 INPUT BUFFER LATCH DAC A RFB A OUT A AGND AGND C12 VOUT A
Table I. Unipolar Binary Code Table
DAC Latch Contents MSB LSB 11111111 10000001 10000000
VOUT B AGND
Analog Output (DAC A or DAC B)
255 -V IN 256 129 -V IN 256 V 128 -V IN = - IN 256 2 127 -V IN 256 1 -V IN 256 0 -V IN =0 256
1 (V ) 256 IN
DAC A/ DAC B CS WR DGND
AD7528
CONTROL LOGIC LATCH DAC B
R41 RFB B OUT B C22
01111111 00000001 00000000
Note: 1 LSB = 2-8 (V IN ) =
R31 VIN B ( 10V) NOTES: 1R1, R2 AND R3, R4 USED ONLY IF GAIN ADJUSTMENT IS REQUIRED. SEE TABLE III FOR RECOMMENDED VALUES. 2C1, C2 PHASE COMPENSATION (10pF-15pF) IS REQUIRED WHEN USING HIGH SPEED AMPLIFIERS TO PREVENT RINGING OR OSCILLATION.
()
Figure 4. Dual DAC Unipolar Binary Operation (2 Quadrant Multiplication); See Table I
VIN A ( 10V) R5 20k R11 R21 VDD DB0 DATA INPUTS DB7 INPUT BUFFER LATCH DAC A RFB A OUT A AGND AGND DAC A/ DAC B CS WR DGND R62 20k R72 10k C13 A1 A2 R11 5k AGND VOUT A
Table II. Bipolar (Offset Binary) Code Table
DAC Latch Contents Analog Output MSB LSB (DAC A or DAC B) 11111111 10000001 10000000 0
1 -V IN 128 127 -V IN 128 128 -V IN 128
1 (V ) 128 IN
127 +V IN 128
AD7528
CONTROL LOGIC LATCH DAC B
R41 RFB B OUT B AGND R31 C23 A3 R92 10k R102 20k A4 R12 5k AGND VOUT B R8 20k
01111111 00000001 00000000
Note: 1 LSB = 2-7 (V IN ) =
VIN B ( 10V) NOTES: 1R1, R2 AND R3, R4 USED ONLY IF GAIN ADJUSTMENT IS REQUIRED. SEE TABLE III FOR RECOMMENDED VALUES. ADJUST R1 FOR VOUT A = 0V WITH CODE 10000000 IN DAC A LATCH. ADJUST R3 FOR VOUT B = 0V WITH CODE 10000000 IN DAC B LATCH. 2MATCHING AND TRACKING IS ESSENTIAL FOR RESISTOR PAIRS R6, R7 AND R9, R10. 3C1, C2 PHASE COMPENSATION (10pF-15pF) MAY BE REQUIRED IF A1/A3 IS A HIGH SPEED AMPLIFIER.
()
Table III. Recommended Trim Resistor Values vs. Grade
Figure 5. Dual DAC Bipolar Operation (4 Quadrant Multiplication); See Table II
Trim Resistor R1; R3 R2; R4
J/A/S 1k 330
K/B/T 500 150
L/C/U 200 82
REV. B
-5-
AD7528
APPLICATIONS INFORMATION Application Hints
To ensure system performance consistent with AD7528 specifications, careful attention must be given to the following points: 1. GENERAL GROUND MANAGEMENT: AC or transient voltages between the AD7528 AGND and DGND can cause noise injection into the analog output. The simplest method of ensuring that voltages at AGND and DGND are equal is to tie AGND and DGND together at the AD7528. In more complex systems where the AGND-DGND intertie is on the backplane, it is recommended that diodes be connected in inverse parallel between the AD7528 AGND and DGND pins (1N914 or equivalent). 2. OUTPUT AMPLIFIER OFFSET: CMOS DACs exhibit a code-dependent output resistance which in turn causes a code-dependent amplifier noise gain. The effect is a codedependent differential nonlinearity term at the amplifier output which depends on VOS (VOS is amplifier input offset voltage). This differential nonlinearity term adds to the R/2R differential nonlinearity. To maintain monotonic operation, it is recommended that amplifier VOS be no greater than 10% of 1 LSB over the temperature range of interest. 3. HIGH FREQUENCY CONSIDERATIONS: The output capacitance of a CMOS DAC works in conjunction with the amplifier feedback resistance to add a pole to the open loop response. This can cause ringing or oscillation. Stability can be restored by adding a phase compensation capacitor in parallel with the feedback resistor.
DYNAMIC PERFORMANCE
ship between input frequency and channel to channel isolation. Figure 7 shows a printed circuit layout for the AD7528 and the AD644 dual op amp which minimizes feedthrough and crosstalk.
SINGLE SUPPLY APPLICATIONS
The AD7528 DAC R-2R ladder termination resistors are connected to AGND within the device. This arrangement is particularly convenient for single supply operation because AGND may be biased at any voltage between DGND and VDD. Figure 8 shows a circuit which provides two +5 V to +8 V analog outputs by biasing AGND +5 V up from DGND. The two DAC reference inputs are tied together and a reference input voltage is obtained without a buffer amplifier by making use of the constant and matched impedances of the DAC A and DAC B reference inputs. Current flows through the two DAC R-2R ladders into R1 and R1 is adjusted until the VREF A and VREF B inputs are at +2 V. The two analog output voltages range from +5 V to +8 V for DAC codes 00000000 to 11111111.
VDD = +15V
DAC A DATA INPUTS CS WR DAC A/DAC B 2 VOLTS R1 10k R2 1k AD584J GND
DB0 DB7
VOUT A = +5V TO +8V SUGGESTED OP AMP: AD644 VOUT B = +5V TO +8V
AD7528
DAC B
VDD
The dynamic performance of the two DACs in the AD7528 will depend upon the gain and phase characteristics of the output amplifiers together with the optimum choice of the PC board layout and decoupling components. Figure 6 shows the relation
-100 -90 ISOLATION - dB -80 -70 TA = +25 C VDD = +15V VIN = 20V PEAK TO PEAK
Figure 8. AD7528 Single Supply Operation
Figure 9 shows DAC A of the AD7528 connected in a positive reference, voltage switching mode. This configuration is useful in that VOUT is the same polarity as VIN allowing single supply operation. However, to retain specified linearity, VIN must be in the range 0 V to +2.5 V and the output buffered or loaded with a high impedance, see Figure 10. Note that the input voltage is connected to the DAC OUT A and the output voltage is taken from the DAC VREF A pin.
VIN (0V TO +2.5V) VOUT VREF A
-60 -50 VDD +15V 20k 50k 100k 200k INPUT FREQUENCY - Hz 500k 1M
DAC A
OUT A
AD7528
Figure 6. Channel-to-Channel Isolation
AD644
V+ PIN 8 OF TO-5 CAN (AD644)
Figure 9. AD7528 in Single Supply, Voltage Switching Mode
3 TA = +25 C VDD = +15V ERROR - LSB 2 NONLINEARITY
V-
AGND
AD7528 PIN 1 C2 LOCATION *NOTE INPUT SCREENS TO REDUCE VREF A* FEEDTHROUGH. DGND LAYOUT SHOWS DAC A/DAC B COPPER SIDE (i.e., BOTTOM VIEW). MSB
C1 LOCATION VREF B* VDD WR CS LSB
1 DIFFERENTIAL NONLINEARITY 2.5 3 3.5 4 5 4.5 5.5 VIN A - Volts 6 6.5 7 7.5
AD7528
Figure 7. Suggested PC Board Layout for AD7528 with AD644 Dual Op Amp
Figure 10. Typical AD7528 Performance in Single Supply Voltage Switching Mode (K/B/T, L/C/U Grades)
-6-
REV. B
AD7528
MICROPROCESSOR INTERFACE
A8-A15 A0-A15 A** VMA ADDRESS DECODE LOGIC A + 1** 2 WR DB0 DB7 D0-D7 DATA BUS *ANALOG CIRCUITRY HAS BEEN OMITTED FOR CLARITY **A = DECODED 7528 ADDR DAC A A + 1 = DECODED 7528 ADDR DAC B ADDRESS BUS DAC A/DAC B CS DAC A WR ALE LATCH 8212 A** ADDRESS BUS DAC A/DAC B CS A + 1** WR DB0 DB7 ADDR/DATA BUS *ANALOG CIRCUITRY HAS BEEN OMITTED FOR CLARITY **A = DECODED 7528 ADDR DAC A A + 1 = DECODED 7528 ADDR DAC B NOTE: 8085 INSTRUCTION SHLD (STORE H & L DIRECT) CAN UPDATE BOTH DACs WITH DATA FROM H AND L REGISTERS DAC A
CPU 8085
ADDRESS DECODE LOGIC
AD7528*
DAC B
CPU 6800
AD7528*
DAC B
AD0-AD7
Figure 11. AD7528 Dual DAC to 6800 CPU Interface
Figure 12. AD7528 Dual DAC to 8085 CPU Interface
PROGRAMMABLE WINDOW COMPARATOR
TEST INPUT 0 TO -VREF VREF A DAC A DATA INPUTS CS WR DAC A/DAC B +VREF DAC B VREF B RFB B
DB0 DB7
VDD RFB A OUT A 3 2 7 VCC 1k
In the circuit of Figure 13 the AD7528 is used to implement a programmable window comparator. DACs A and B are loaded with the required upper and lower voltage limits for the test, respectively. If the test input is not within the programmed limits, the pass/fail output will indicate a fail (logic zero).
AD7528
AD311 COMPARATOR OUT B 2 3
PASS/ FAIL OUTPUT
7
AD311 COMPARATOR
Figure 13. Digitally Programmable Window Comparator (Upper and Lower Limit Detector)
PROGRAMMABLE STATE VARIABLE FILTER
In this state variable or universal filter configuration (Figure 14) DACs A1 and B1 control the gain and Q of the filter characteristic while DACs A2 and B2 control the cutoff frequency, fC . DACs A2 and B2 must track accurately for the simple expression for fC to hold. This is readily accomplished by the AD7528. Op amps are 2 x AD644. C3 compensates for the effects of op amp gain bandwidth limitations.
R5 30k R4 30k C1 1000pF
The filter provides low pass, high pass and band pass outputs and is ideally suited for applications where microprocessor control of filter parameters is required, e.g., equalizer, tone controls, etc. Programmable range for component values shown is fC = 0 kHz to 15 kHz and Q = 0.3 to 4.5.
CIRCUIT EQUATIONS
C2 1000pF
C1 = C 2, R1 = R2, R4 = R5
LOW PASS OUTPUT
R3 10k A1
C3 47pF HIGH PASS OUTPUT
A2
A3 BAND PASS OUTPUT
A4
VDD
VDD
AD7528
VIN DAC A1 RS DAC B1 RF DAC A2 R1
AD7528
DAC B2 R2
1 2 R1C1 R3 RF Q= x R4 RFBB1 RF AO = - RS fC =
NOTE DAC Equivalent Resistance Equals
256 x ( DAC Ladder Resistance ) DAC Digital Code
DB0-DB7 DATA 1 CS WR DAC A/DAC B
DB0-DB7 DATA 2 CS WR DAC A/DAC B
Figure 14. Digitally Controlled State Variable Filter
REV. B
-7-
AD7528
DIGITALLY CONTROLLED DUAL TELEPHONE ATTENUATOR
In this configuration the AD7528 functions as a 2-channel digitally controlled attenuator. Ideal for stereo audio and telephone signal level control applications. Table IV gives input codes vs. attenuation for a 0 dB to 15.5 dB range. Input Code = 256
VDD VIN A DAC A A1
DB0 DB7
Table IV. Attenuation vs. DAC A, DAC B Code for the Circuit of Figure 15
Attn. DAC Input dB Code 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 11111111 11110010 11100100 11010111 11001011 11000000 10110101 10101011 10100010 10011000 10010000 10001000 10000000 01111001 01110010 01101100 Code In Decimal 255 242 228 215 203 192 181 171 162 152 144 136 128 121 114 108 Attn. DAC Input dB Code 88.0 88.5 89.0 89.5 10.0 10.5 11.0 11.5 12.0 12.5 13.0 13.5 14.0 14.5 15.0 15.5 01100110 01100000 01011011 01010110 01010001 01001100 01001000 01000100 01000000 00111101 00111001 00110110 00110011 00110000 00101110 00101011 Code In Decimal 102 96 91 86 81 76 72 68 64 61 57 54 51 48 46 43
C681e-0-9/98 PRINTED IN U.S.A.
10 exp -
Attenuation, dB 20
VOUT A
DATA BUS CS WR DAC A/DAC B VIN B
AD7528
VOUT B
A2
DAC B
SUGGESTED OP AMP: AD644
Figure 15. Digitally Controlled Dual Telephone Attenuator
For further applications information the reader is referred to Analog Devices Application Note on the AD7528.
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
20-Lead Cerdip (Q-20)
20 11
20-Lead Plastic DIP (N-20)
1.07 (27.18) MAX
PIN 1
1 10
0.28 (7.11) 0.24 (6.1) 0.97 (24.64) 0.935 (23.75) 0.32 (8.128) 0.29 (7.366) 0.14 (3.56) 0.125 (3.17) SEATING PLANE 0.145 (3.683) MIN 0.125 (3.175) MIN 0.011 (0.28) 0.009 (0.23)
20 1
11 10
0.255 (6.477) 0.245 (6.223)
PIN 1 0.135 (3.429) 0.125 (3.17)
0.32 (8.128) 0.30 (7.62)
0.20 (5.0) 0.14 (3.56) 0.15 (3.8) 0.125 (3.18)
0.07 (1.78) 0.02 (0.5) 0.11 (2.79) 15 0.05 (1.27) 0.016 (0.41) 0.09 (2.28) 0 LEAD NO. 1 IDENTIFIED BY DOT OR NOTCH LEADS ARE SOLDER OR TIN-PLATED KOVAR OR ALLOY 42
SEATING 0.011 (0.28) 0.11 (2.79) 0.065 (1.66) PLANE 0.021 (0.533) 15 0.009 (0.23) 0.09 (2.28) 0.045 (1.15) 0 0.015 (0.381) LEAD NO. 1 IDENTIFIED BY DOT OR NOTCH LEADS ARE SOLDER OR TIN-PLATED KOVAR OR ALLOY 42
20-Lead SOIC (R-20)
0.5118 (13.00) 0.4961 (12.60)
20
20-Lead Plastic Leaded Chip Carrier (P-20A)
0.395 (10.02) SQ 0.385 (9.78) 0.356 (9.04) 0.350 (8.89) SQ 0.048 (1.21) 0.042 (1.07)
3 4 19
PIN 1 IDENTIFIER
0.180 (4.47) 0.165 (4.19) 0.12 (3.05) 0.09 (2.29) 0.020 (0.51) MIN 0.021 (0.53) 0.013 (0.33) 0.032 (0.81) 0.026 (0.66)
11
0.2992 (7.60) 0.2914 (7.40)
1 10
0.4193 (10.65) 0.3937 (10.00)
18
TOP VIEW
(PINS DOWN)
0.050 (1.27) BSC
PIN 1
0.1043 (2.65) 0.0926 (2.35)
0.0291 (0.74) 0.0098 (0.25)
45
8 0.02 9 (0.51) MAX 0.02 (0.51) MAX
14 13
0.025 (0.64) MIN 0.060 (1.53) MIN
0.0118 (0.30) 0.0040 (0.10)
8 0.0500 0.0192 (0.49) SEATING 0 (1.27) 0.0138 (0.35) PLANE 0.0125 (0.32) BSC 0.0091 (0.23)
0.0500 (1.27) 0.0157 (0.40)
-8-
REV. B

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